The present invention relates to a stack package, and more particularly, to a stack package using re-distribution lines and solder balls.
As the performances of electric and electronic products are improved, techniques for mounting an increased number of packages to a substrate having a limited size have been researched. Generally, in a stack package, one semiconductor chip is mounted to a substrate, which increases the difficulty of attaining a desired capacity.
As a method of increasing the capacity of a memory chip, that is, for accomplishing high integration, it is generally known in the art that an increased number of cells are formed in a limited space. However, this method requires use of high-precision process techniques involving a fine design rule and results in a substantially longer development time. Accordingly, a stacking technology has been developed as a method for easily realizing high integration, and research for the stacking technology has been active.
As used in the semiconductor industry, the term “stacking” means to vertically arrange at least two semiconductor chips to increase memory capacity. For example, by stacking two 256M DRAM chips, 512M DRAM can be configured in a single package. In addition, stacking technology provides advantages in mounting density and mounting area utilization efficiency.
With respect to stacking at least two semiconductor chips, a method in which at least two semiconductor chips are stacked in one package, and a method in which at least two packages are stacked, are known in the art.
FIG. 1 is a cross-sectional view illustrating the conventional stack package manufactured by the first method. Referring to FIG. 1, three semiconductor chips 110, 120 and 130, of different sizes that possess bonding pads 112, 122 and 132 on the peripheral portions thereof, are stacked on a printed circuit board (hereinafter referred to as “PCB”) 100. The bonding pads 112, 122 and 132 of the respective semiconductor chips 110, 120 and 130 and the circuit patterns 102 of the PCB 100 are connected to each other by metal wires 140. The upper surface of the PCB 100, including the semiconductor chips 110, 120 and 130 and the metal wires 140, is molded by a molding material 150. Solder balls 160, providing electrical connections to external circuits, are attached to the lower surface of the PCB 100.
However, in the conventional stack package resulting from the construction method described above, since the bonding pads 112, 122 and 132 are formed on the peripheral portions of the semiconductor chips 110, 120 and 130 and connected to the circuit patterns 102 of the PCB 100 by the metal wires 140, same-size semiconductor chips cannot be stacked unless a tape containing a shock-absorbing substance is interposed between two adjoining semiconductor chips. Furthermore, because the electrical connections in a conventional stack package are formed by the metal wires 140, it is difficult to apply the stack package in high-speed products. Moreover, the presence of wire loops in the conventional stack package increases the size of the package.